library ieee;
use ieee.std_logic_1164.all;

--I0 will be the output if S is 0
--I1 will be the output if S is 1
entity mux2to1 is
	port (I0, I1, S : in bit;
        F : out bit);
end entity mux2to1;

architecture DATAFLOW of mux2to1 is
    
    signal andOut : bit_vector(1 downto 0);
    
    begin
        
        andOut(0) <= I0 and (not S);
        andOut(1) <= I1 and S;
        
       	F <= andOut(0) or andOut(1);
		
end architecture DATAFLOW;

architecture STRUCTURAL of mux2to1 is

component and2
	port( 
	a,b : in bit;
	z : out bit
	);
end component;
component or2
	port (
	a,b : in bit;
	z : out bit
	);
end component;
component not1
	port (
	a : in bit;
	z : out bit	
	);
end component;	

	for all : and2 use entity work.and2(DATAFLOW);
	for all : or2 use entity work.or2(DATAFLOW);
	for all : not1 use entity work.notDataFlow(DATAFLOW);
	
	signal  and_out : bit_vector(1 downto 0);
	signal Snot : bit;

begin

	invert : not1 port map(S, Snot);
	and_0 : and2 port map (I0, Snot, and_out(0));
	and_1 : and2 port map (I1, S, and_out(1));
	or_0 : or2 port map(and_out(0), and_out(1), F);


end architecture STRUCTURAL;